In producing integrated circuits to drive high current outputs, it is often desirable to monitor the current being driven through a particular device and to limit this current so that no damage occurs to the driving device.
Various prior art approaches to this problem exist. FIGS. 1, 2 and 3 are schematics of three prior art current limiting circuits. In FIG. 1, transistor M1 is an NMOS power transistor which is connected between the low-potential side of a load and ground. This configuration is usually called a low-side-drive (hereinafter LSD) configuration. The NMOS transistor M1, when enabled by the output of set-reset flip-flop FF1, will pull an output terminal OUT to a low voltage. A small resistor R1 is inserted between M1's source and ground. When the set-reset flip flop FF1 is set by a voltage pulse at the input terminal Vin, the Q output enables transistor M1 to conduct. Some current flows through the transistor and into resistor R1. The voltage developed across this resistor is proportional to the current flowing through the M1 transistor's source. When this voltage exceeds a threshold voltage V1, comparator C1 trips and resets flip-flop FF1, turning off the power transistor to protect it against excessive current flow. There are many variations on this circuit, including ones where the flip-flop FF1 is replaced by various timing circuits, and circuits where the resistor is placed in the drain of the power transistor rather than in the source. There are also prior art circuits where the inherent resistance of the power device is used as a sense resistor, eliminating the need for a separate sense resistor R1.
FIG. 2 depicts the use of the approach of FIG. 1 in a high-side-drive (hereinafter HSD) situation. Now the output transistor M1 attempts to pull an output node high when enabled. Terminal OUT is coupled to the load and will be pulled up dose to the voltage Vcc when the gate of PMOS transistor M1 is enabled by FF1. As before, the current is sensed by the small resistor R1 which creates a voltage proportional to the current flowing through the output transistor M1. The comparator C1 trips when the current flowing through R1 causes the voltage across R1 to exceed the reference voltage V1, and the flip flop is reset causing the output transistor M1 to cut off, thereby protecting the output transistor.
The main difficulty in realizing the current limit schemes of FIGS. 1 and 2 is the common-mode range required of the comparator. In the low-side-drive configuration of FIG. 1, the comparator's common-mode range must include ground. In the high-side-drive configuration of FIG. 2, the comparator's common-mode range must include the supply. For this reason, many existing implementations of current-limit circuits use emitter-side comparators as alternatives to the conventional comparators depicted in the prior art circuits of FIGS. 1 and 2.
A prior art current limit circuit based on a simple emitter-side comparator is shown in FIG. 3. As before, the current through power transistor M1 is sensed by the insertion of a resistor R1 between source and ground. Current flowing through R1 develops a voltage potential V1. A pair of NPN transistors Q1 and Q2, having equal emitter areas, form the comparator. Transistor Q2 is diode-connected, and a current source I2, providing a relatively small but constant current, is connected so as to feed the collector-base side of Q2. The emitter of Q2 is connected through resistor R2 to ground.
In operation the circuit of FIG. 2 compares the current flowing through resistor R1, which is proportional to the current flowing in the output transistor M1, to the current flowing in resistor R2. If base current errors are neglected, the potential developed across R2 is just V2=I2*R2. If voltage V1=V2, then the emitter current which Q1 can support will be equal to that which Q2 can support. Thus, if a current source I1 is connected to the collector of Q1, such that I1=I2, Q1 will just be able to sink this current when V1=V2. If V1&lt;V2, Q1 will attempt to sink more current than I1 can provide, and V3 will go low (Q1 will saturate). If V1&gt;V2, Q1 will not be able to sink all of the current provided by I1, and V3 will go high (Current source I1 will saturate). Therefore, Q1 and Q2 form a comparator with a trip point when V1=V2. Because the voltages to be compared are present at the emitters of the NPN transistors, this configuration is sometimes called an emitter-side comparator or emitter-sensing comparator. The current limit that this comparator provides is simply: EQU I.sub.LIMIT =R2/(R1*I2) (1)
A minor problem with the operation of the circuit of FIG. 3 as described above is that transistor Q1 is normally saturated, and must come out of saturation when the current limit is exceeded. Stored charge in Q1 will cause substantial delay in the comparator's action. This can be cured by using a Schottky clamp on Q1, as is shown in FIG. 3 by the cuffed ends on the transistor Q1's base.
Several assumptions are made in the analysis which led to equation (1). First, I1 (and therefore I2 as well) are assumed to be much smaller than the current drawn by the load. If this is not true, then the value of R1 must be adjusted to compensate for the IR drop caused by I1. The assumption that I1&lt;&lt;IL is usually a fairly good assumption, as load currents are usually 100 mA or more, and the transistors Q1 and Q2 can be run at a small fraction of a milliamp. Another assumption is that the base current error caused by Q1 does not unbalance the currents IR1 and IR2. If transistor betas are low, a base current cancellation technique can be used to eliminate the base current errors.
Another assumption which is implicit in the circuit of FIG. 3 is that resistors R1 and R2 are well-matched. R1 is usually much smaller than R2. For example, suppose a 1 Amp current limit is desired, and the emitter-side comparator is fed 10 microamps per side. The two resistors now differ in value by five orders of magnitude! Such an enormous mismatch implies difficulty in constructing well-matched resistors. In order to conserve space, the two resistors are often fabricated using very different materials so as to provide different resistivities. If this is done, matching becomes very difficult to maintain over the expected ranges of temperature and process variations. Also, the current source supplying the current I2 is critical to the operation of the circuit, because the threshold at which the current limiting begins is directly proportional to I2. The circuit will therefore exhibit a considerable dependence on temperature and process variations, and the current sources will have to be fairly complex circuits to provide stable currents I1 and I2 in spite of these variations.
The current limiting schemes of the prior art have limitations that do not make them well suited for integrated circuit applications. Thus there is a need for an improved current limiting scheme for use in power integrated circuits and systems.